nVidia G80
Napsal: sob úno 04, 2006 12:11 pm
Není známo, jestli se to týká G80, nebo až nějaké další generace, ale je to zajímavé... 
Jaws píše:I thought I'd post a thread here (after being told off!) about a patent I posted in the console tech a while ago,
NVIDIA Patent: G70/G80/RSX?
Programmable graphics processor for generalized texturing
It describes a unified shader unit with a coupled texture unit. The texture unit has sub-units that are multi-threaded. These specialised sub-units could be used in combination for a desired result and therefore increase untilisation. Effectively the unified shader unit is a multi-threaded processor. They also discuss removing ROPs completely so that the unified shader unit could act as a 'programmable' ROP...
Here's a pic of the unit... thoughts?
xbdestroya píše:I think it's worth posting one of the '240s' as well, just for some context. Whether G80 ends up related to this patent or not, I think the fact that this patent itself describes a unified shader architecture is fairly evident.
With some select quotes from the patent:In a typical implementation Programmable Graphics Processing Pipeline 150 performs geometry computations, rasterization, and fragment computations. Therefore Programmable Graphics Processing Pipeline 150 is programmed to operate on surface, primitive, vertex, fragment, pixel, sample or any other data. For simplicity, the remainder of this description will use the term "samples" to refer to graphics data such as surfaces, primitives, vertices, pixels, fragments, or the like.FIG. 3 is an illustration of an exemplary embodiment of Execution Pipeline 240 containing at least one Multithreaded Processing Unit 300 in accordance with one or more aspects of the present invention. An Execution Pipeline 240 can contain a plurality of Multithreaded Processing Units 300, each Multithreaded Processing Unit 300 containing an Execution Unit 370. Each Execution unit 370 includes at least one PCU 375. PCUs 375 are configured using program instructions read by a Thread Control Unit 320 via a dedicated Read Interface 205. In an alternate embodiment Read Interface 205 is shared between two or more Multithreaded Processing Units 300. Thread Control Unit 320 gathers source data specified by the program instructions and dispatches the source data and program instructions to at least one PCU 375. PCUs 375 perform computations specified by the program instructions and outputs data to at least one destination, e.g., Pixel Output Buffer 270, Vertex Output Buffer 260 or Register File 350.
trinibwoy píše:I read this patent when it first appeared in console and just re-read it again. One thing that stands out to me is that the threading and arbitration logic is implemented at the pipeline level and there isn't a master scheduler like in Xenos.
The other thing is the extra level of nesting of processing elements.
Pipeline (Shader) -> Multi-threaded processing unit(s) MPU(s) -> Execution Unit -> PCU(s).
A PCU looks to be just what we call an ALU today. What I don't get is why you would need multiple MPU's in a pipeline ? ILP is handled through more PCU's. TLP can be handled by a single MPU. What benefit is there to having multiple MPU's per shader as opposed to more shaders with a single MPU each?






