Datasheet text preview:
ICS5342 GENDAC 16-Bit Integrated Clock-LUT-DAC
General Description
The ICS5342 GENDAC is a combination of dual programmable clock generators, a 256 x 18-bit RAM, and a triple 8-bit video DAC. The GENDAC supports 8-bit pseudo color applications, as well as 15-bit, 16-bit, and 24-bit True Color bypass for high speed, direct access to the DACs. The RAM makes it possible to display 256 colors selected from a possible 262,144 colors. The dual clock generators use Phase Locked Loop (PLL) technology to provide programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, all of which are programmable by the user. The memory clock has two programmable frequency locations. The three 8-bit DACs on the ICS5342 are capable of driving singly or doubly-terminated 75 loads to nominal 0 - 0.7 volts at pixel rates up to 135 MHz. Differential and integral linearity errors are less than 1 LSB over full temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather than by modifying the color palette. ICS is the world leader in all aspects of frequency (clock) generation for graphics, using patented techniques to produce low jitter video timing.
Features
   Triple video DAC, dual clock generator, and 16 bit pixel port Dynamic mode switch allows switching of color depth on a pixel by pixel basis 24 (packed and sparse), 16, 15, or 8-bit pseudo color pixel mode supports True Color, Hi-Color, and VGA modes High speed 256 x 6 x 3 color palette (135 MHz) with bypass mode and 8-bit DACs Eight programmable video (pixel) clock frequencies (CLK0) DAC power down in blanking mode Anti-sparkle circuitry On-chip loop filters reduce external components Standard CPU interface Single external crystal (typically 14.318 MHz) Monitor sense Internal voltage reference 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions Very low clock jitter Two latched frequency select pins or three non-latched frequency select pins (programmable) Hardware video checksum for manufacturing tests
            
Block Schematic
PCLK COMPARE 24 P0-P15 BUFF. LATCH A PIXEL ADR MND ASK D0-D7 WR* RD* RS0-RS2 STROBE CS0-CS2 BLANK* 16 P MICROIROCESSOR NTERFACE 8 16 TG ING IM EN.
CTL 8 PLL PARAMETER & CLK0 PLL 1 PLL PARAMETER & CLK1 PLL BYPS
SENSE* RED GREEN BLUE RSET VREF
P OLOR C 2ALETTE 56 x 18 BIT
MUX 18
NORM
LATCH
24
TRIPLE 6 /8-BIT D AC
MUX.
PCLK
2X MODE CLK0
XIN
XTAL O SC
XOUT
CLK1 5342_01.ai
REV. 0.9.0
ICS5342 GENDAC
Pin Configuration Pin Configuration
CGND CLK1 P14 15 D0 D1 D2 D3 D4 5 D6 D7 WR* RS0 S1 MSW CGND 10 11 12 13 14 15 16 17 18 29 20 21 22 23 24 25 6
P CVDD P CL K0 P BL ANK* STROBE* RD* 13 CS1 P S0 12 SENSE* P1 1 10 9 N P8 RS2 /C CVDD 9 8 7 6 5 4 3 2 1 68 67 66 65 4 63 62 1
GENDAC II ICS5342
5 60 9 58 57 56 55 54 53 52 51 40 49 48 47 46 45 4
0 41 42 3
P CGND CLK P7 6 P5 P4 P3 P2 P1 X0 VDD XOUT IN XGND N VREF D/C GND
CVDD N/C N/C N/C N/C /C N/C N/C /C AGND RED GRN /C BLUE AVDD RSET DVDD
4 27 28 29 30 31 32 33 34 35 36 4 37 38 39
5342_02
ICS5342 (68-pin PLCC)
Pin Description (68-pin PLCC)
Symbol D7 - D0 Pin # 21-14 Type I/O Description Systems data bus bidirectional data I/O lines  used by host microprocessor for internal register read and write operations (using active low RD and WR respectively) for six internal registers: Pixel Address, Color Value, Pixel Mask, PLL Address, PLL Parameter, and Command During the write cycle, the rising edge of WR latches the data into the selected register (set by the status of the three RS pins). The rising edge of RD determines the end of the read cycle. The RD set logical high indicates that data I/O lines no longer contain information from the selected register and will be tri-stated. RAM/PLL read enable bus control signal  in active low state, any information present on the internal data bus is available on the Data I/O lines, D0-D7 Active low RAM/PLL write enable bus control signal  controls write timing on microprocessor interface inputs, D0-D7 Register address select 0 inputs  control selection of one of six internal registers  inputs are sampled on falling edge of active enable signal (RD or WR) Crystal input  connect to 14.318 MHz crystal Crystal output  connect to 14.318 MHz crystal Mode switch  digital control for selecting primary and secondary pixel color modes  low selects primary mode  connect to ground if not used
RD WR RS2-RS0 XIN XOUT MSW
5 22 63,24,23 48 49 25
Input Input Input Input Output Input
2
ICS5342 GENDAC
Pin Description (68-pin PLCC)
Symbol CLK1 CLK0 CS0 CS1 VREF RSET SENSE* Pin # 11 8 2 3 46 42 68 Type Output Output Input Input I/O Input Output Description Memory clock output  used to time video memory Video clock output  provides a CMOS level pixel or dot clock frequency to graphics controller  output frequency is determined by values of PLL registers Clock select 0  The status of CS0-1 determines which frequency is selected on the CLK0 (video) output. Clock select 1 status of CS0-1 determines which frequency is selected on CLK0 (video) output Internal reference voltage  normally connects to a 0.1f capacitor to ground  to use external Vref, connect 1.235V reference to this pin Resistor set  pin used to set current level in analog outputs  usually connected through 1/4W, 1% resistor to ground Monitor sense  Pin is active low when any of red, green, or blue outputs >385mV. Sense output is high when all analog outputs are < 275 mV. Chip has on-board comparators and internal 1.235 V voltage reference. This signal is used to detect monitor type. Color signals from DAC analog outputs  Each DAC comprises several current sources of which outputs are added together according to the applied binary value. The outputs are typically used to drive a CRT monitor. Pixel address lines  Byte-wide information is latched by the rising edge of PCLK when using the color palette, and is masked by the Pixel Mask register. Values are used to specify the RAM word address in default mode (accessing RAM). In HiColor XGA, and True Color modes, they represent color data for the DACs. Ground inputs if they are not used. Pixel Clock  rising edge of PCLK controls latching of the Pixel Address and BLANK* inputs  clock also controls progress of these values through the threestage pipeline of the Color Palette RAM, DAC, and outputs latches input clock select signals CS0-CS1 Composite BLANK* Signal, active low. When BLANK* is asserted, outputs of DACs are zero which blacks screen. DACs are automatically powered down to save current during blanking. Color palette may still be updated through D0-D7 during blanking. CLK1 Power Supply  connect to DVDD CLK0 power supply  connect to AVDD DAC power supply  Connect to AVDD Digital power supply Crystal oscillator power supply connect to AVDD CLK power supply  connect to DVDD VSS for CLK1  connect to ground. VSS for CLK0  connect to ground VSS for crystal oscillator DAC ground  connect to ground Digital ground  connect to ground VSS for CLK  connect to ground Not connected  leave floating or tie to ground
BLUE GREEN RED P15- P0
40 38 37 13,12,4,1 , 67-64, 58-51 59
Output Output Output Input
PCLK
Input
STROBE* BLANK*
6 7
Input Input
CVDD CVDD AVDD DVDD XVDD CVDD CGND CGND XGND AGND DGND CGND N/C
9 27 41 43 50 61 10 26 47 36 44 60 28-35, 39,45, 62
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3 